1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device including a resistor and an active component such as a bipolar transistor and a Field-Effect Transistors (FET), and a fabrication method of the device.
2. Description of the Prior Art
With the fabrication of a semiconductor device termed a "gate array", a semiconductor substrate including active and passive components therein is prepared in advance. The components are arranged in the form of an array. Then, customized interconnection layers are formed on or over the active and/or passive components to electrically interconnect the related components. Thus, an integrated circuit device having specific functions is fabricated according to the need of a customer.
FIG. 1 shows a schematic plan view of a resistor used for the semiconductor device of this sort.
In FIG. 1, the resistor is made of a patterned polysilicon layer 121 with a rectangular plan shape. The layer 121 is doped with an n- or p-type impurity to realize a wanted conductivity. Two contact areas 122 are formed on the layer 121 near its opposite ends, respectively. The width of the layer 121 is W, and the distance between the contact areas 122 is L.
When the sheet resistance of the doped polysilicon layer 121 is defined as .rho..sub.s, and the contact resistance of the layer 121 at the contact areas 122 is defined as R.sub.c, the resistance R of the polysilicon resistor is expressed as the following equation (1). EQU R=.rho..sub.s (L/W)+2R.sub.c (1)
A conventional semiconductor device including the polysilicon resistor of FIG. 1 is shown in FIG. 2, which is, for example, disclosed in the Japanese Non-Examined patent Publication No. 3-22562 published in January 1991. Although this semiconductor device has a plurality of bipolar transistor regions and a plurality of resistor regions, only one bipolar transistor region and only one resistor region are explained here for the sake of simplification.
As shown in FIG. 2, this semiconductor device includes a bipolar transistor region 130 having an npn-type bipolar transistor and a resistor region 131 having a resistor.
An n-type single-crystal silicon (Si) epitaxial layer 104 is formed on the surface of a p-type single-crystal silicon substrate 101. An n-type buried layer 102 is formed near the interface of the substrate 101 and the epitaxial layer 104. A p-type insulating layer 103 is selectively formed in the epitaxial layer 104. The bottom of the layer 103 is extended to the inside of the substrate 101.
A field oxide layer 105 of silicon dioxide (SiO.sub.2) is selectively formed in the surface are of the epitaxial layer 104 for electrical isolation. The bipolar transistor region 130 is electrically isolated from the resistor region 131 and other device regions (not shown) adjacent to the region 130.
In the transistor region 130, an n.sup.+ -type collector connection region 106, a p-type extrinsic base region 107, and a p-type intrinsic base region 108, an n-type emitter region 109 are formed in the epitaxial layer 104.
A SiO.sub.2 layer 110 is formed on the field oxide layer 105 and the exposed epitaxial layer 104. A contact window 124 is formed in the SiO.sub.2 layer 110 to expose the underlying emitter region 109.
An n-type polysilicon emitter contact region 111 is selectively formed on the SiO.sub.2 layer 110 to be contacted with the emitter region 109 through the window 124 in the transistor region 130. The emitter contact region 111 is doped with arsenic (As). The As-doped region 111 serves as a diffusion source of the n-type impurity As during the thermal diffusion process of forming the n-type emitter region 109.
An n-type polysilicon resistor layer 121 is selectively formed on the SiO.sub.2 layer 110 in the resistor region 131. The resistor layer 121 also is doped with As, and serves as the resistor as shown in FIG. 1. The doping concentration of As in the layer 121 is set at a value that enables a wanted resistance.
A SiO.sub.2 layer 112 and a Boro-Phospho-Silicate Glass (BPSG) layer 113 are successively formed on the SiO.sub.2 layer 110 to cover the n-type polysilicon emitter contact 111 and the n-type polysilicon resistor layer 121.
A contact hole 125 is formed to vertically penetrate the BPSG layer 113, the SiO.sub.2 layer 112, and the SiO.sub.2 layer 110 in the transistor region 130. The contact hole 125 is located above the extrinsic base region 107 and exposes the underlying region 107.
A contact hole 126 is formed to vertically penetrate the BPSG layer 113 and the SiO.sub.2 layer 112 in the transistor region 130. The contact hole 126 is located above the emitter contact region 111 and exposes the underlying region 111.
Two contact holes 123 are formed to vertically penetrate the BPSG layer 113 and the SiO.sub.2 layer 112 in the resistor region 131. The contact hole 123 are located above the resistor layer 121 and exposes the underlying layer 121.
Barrier metal layers 114 are selectively formed in the contact holes 123, 125, 126 to cover the sides and bottoms of the holes 123, 125, 126, respectively. The layer 114 in the hole 125 is contacted with the extrinsic base region 107. The layer 114 in the hole 126 is contacted with the emitter contact region 111. The two layers 114 in the hole 123 are contacted with the polysilicon resistor layer 121, respectively.
Tungsten (W) layers 115 are selectively formed on the corresponding barrier metal layers 114 in the contact holes 123, 125, 126, respectively. The W layers 115 bury the corresponding holes 123, 125, and 126. In other words, the W layers 115 serve as conductor plugs, respectively.
Wiring or interconnection layers 116 made of an alloy of AlSiCu are selectively formed on the corresponding barrier layers 114 and the corresponding W layers 115, respectively.
The conventional semiconductor device of FIG. 2 is fabricated in the following way:
First, as shown in FIG. 3A, the n-type single-crystal Si epitaxial layer 104, the n-type buried layer 102, the p-type insulating layer 103, the field oxide layer 105 of SiO.sub.2, the n.sup.+ -type collector connection region 106, the p-type extrinsic base region 107, and the p-type intrinsic base region 108, and the n-type emitter region 109 are formed on the p-type single-crystal Si substrate 101 with the use of known process steps.
Then, the SiO.sub.2 layer 110 with a thickness of 150 to 400 nm is formed on the field oxide layer 105 and the exposed epitaxial layer 104 by using, for example, a Chemical Vapor Deposition (CVD) process.
The contact window 124 is formed in the SiO.sub.2 layer 110 by using photolithography and dry etching processes, thereby exposing the underlying the intrinsic base region 108.
Subsequently, a polysilicon layer (not shown) with a thickness of approximately 330 nm is formed on the SiO.sub.2 layer 110 by using, for example, a Low-Pressure CVD process. This polysilicon layer may be formed by a sputtering process. In this case, this layer becomes amorphous. This means that the polysilicon layer may be replaced with an amorphous silicon layer.
A part of the polysilicon layer thus formed, which serves as the impurity source for the formation process of the n-type emitter region 109, is selectively doped with As by an ion-implantation process at an acceleration energy of 50 keV to 100 keV with a dose of 1.times.10.sup.16 atoms/cm.sup.2. Further, while masking the As doped part of the polysilicon layer, the remaining part of the polysilicon layer is selectively doped with boron (B) by an ion-implantation process at an acceleration energy of 30 keV with a dose of 6.times.10.sup.14 atoms/cm.sup.2. The acceleration energy and the dose of the second ion-implantation process are determined to realize a wanted, predetermined sheet resistance and a wanted, predetermined contact resistance in the resistor region 130.
The polysilicon layer thus ion-implanted twice is then patterned by photolithography and dry etching processes; thereby forming the n-type polysilicon emitter contact region 111 and the p-type polysilicon resistor region 121. The state at this stage is shown in FIG. 3A.
The n-type polysilicon emitter contact region 111 is contacted with the intrinsic base region 108 through the window 124 in the transistor region 130. The p-type polysilicon layer 121 is contacted with the SiO.sub.2 layer 110 in the resistor region 131.
Following this patterning process, the SiO.sub.2 layer 112 with a thickness of approximately 200 nm and the BPSG layer 113 with a thickness of approximately 1000 nm are successively formed on the SiO.sub.2 layer 110 to cover the n-type polysilicon region 111 and the p-type polysilicon region 121.
The device assembly thus prepared is subjected to a heat treatment at a temperature of 950.degree. C. for approximately 20 minutes. Through this heat-treatment process, the implanted As atoms in the emitter contact region 111 are thermally diffused into the intrinsic base region 108, resulting in the n-type emitter region 109 therein. At the same time as this diffusion process, the BPSG layer 113 is reflown, resulting in the planarized surface of the layer 113. The state at this stage is shown in FIG. 3B.
Further, the BPSG layer 113 thus reflown and the underlying SiO.sub.2 layers 112 and 110 are patterned by photolithography and dry etching processes, thereby forming the contact hole 125.
Through the similar ways, the contact hole 126 is formed in the BPSG layer 113 and the SiO.sub.2 layer 112 in the transistor region 130, and the contact holes 123 are formed in the BPSG layer 113 and the SiO.sub.2 layer 112 in the resistor region 131.
A metal layer (not shown) serving as the barrier metal layers 114 is deposited by a CVD process. This metal layer has a two-layer structure made of a lower titanium (Ti) sublayer with a thickness of 5 nm and an upper titanium nitride (TiN) sublayer with a thickness of 100 nm.
A W layer (not shown) with a thickness of 1000 nm is deposited on the metal layer by a CVD process. Then, the metal layer and the W layer are etched back to selectively remove these layers, thereby leading the barrier metal layers 114 in the contact holes 123, 125, 126, and the W layers 115 on the corresponding barrier metal layers 114, respectively.
An AlSiCu layer (not shown) with a thickness of 800 nm is deposited by a CVD process and then, is patterned by photolithography and dry etching processes. Thus, the wiring AlSiCu layers 116 are selectively formed on the corresponding W layers 115, respectively.
Finally, the semiconductor assembly thus obtained is subjected to a heat treatment for an annealing purpose at a temperature of 430.degree. C. for approximately 30 minutes. Thus, the conventional semiconductor shown in FIG. 2 is finished.
With the conventional semiconductor device shown in FIG. 2, to reduce the area of the resistor region 131, contact resistance between the polysilicon layer 112 and the metal barrier layer 123 is used. This point is explained in detail below with reference to FIG. 4 showing the contact area dependence of the contact resistance.
The arsenic-doped polysilicon layer 121 formed by the above-described processes has a sheet resistance of approximately 700 .OMEGA./sq. It is seen from the line B in FIG. 4 that the contact resistance R.sub.c between the polysilicon layer 121 and the metal barrier metal 114 is approximately 700 .OMEGA./sq at the contact area of 4 .mu.m.sup.2 (=2 .mu.m.times.2 .mu.m), which is very high. Also, the contact resistance R.sub.c has a small fluctuation.
As a result, if a resistor whose resistance R is 3.5 k.OMEGA. is formed by the polysilicon layer 121 with the contact area of 4 .mu.m.sup.2 (=2 .mu.m.times.2 .mu.m), the length L of the resistor is expressed as the following equation (2). EQU L=(3500-700.times.2).times.4.times.(1/700)=12 .mu.m (2)
On the other hand, if the metal barrier layer 114 is not used, it is seen from the line A in FIG. 4 that the contact resistance R.sub.c between the polysilicon layer 121 and the W layer 115 is approximately 70 .OMEGA./sq at the contact area of 4 .mu.m.sup.2 (=2 .mu.m.times.2 .mu.m), which is very low. Therefore, the length L of the resistor is expressed as the following equation (3). EQU L=(3500-70.times.2).times.4.times.(1/700)=19.2 .mu.m (3)
As seen from the equations (2) and (3), with the conventional semiconductor device shown in FIG. 2, the necessary area of the resistor can be reduced compared with the case of no barrier metal layer by approximately 40%.
However, the improvement by the above conventional semiconductor device in FIG. 2 is insufficient for the gate arrays, the reason of which is as follows.
For general-purpose semiconductor devices such as memories and microprocessors, the chip area is able to be reduced by carefully designing the layout of the devices and/or their interconnections if the improvement of the conventional semiconductor device in FIG. 2 is applied.
On the other hand, for the gate arrays, a plurality of passive components such as resistors and a plurality of active components such as transistors are prepared in advance on the semiconductor substrate, and than, the interconnection layers are formed on the active and passive components to realize the circuit functions required by a customer. Therefore, part of the prepared resistors may not be practically used according to the required circuit configuration. This causes the necessary chip area to be increased.